HD6417750RF240V Datasheet, PDF (82/606 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 2 CPU
Table 2.13 Effective Address Calculation
No Addressing Mode and Instruction Format
1 Register direct (Rn)
op rm rn
2 Register indirect (@ERn)
op
r
3 Register indirect with displacement
@(d:16,ERn)/@(d:32,ERn)
op
r
disp
Effective Address Calculation
31
0
General register contents
31
0
General register contents
31
Sign extension
0
disp
4 Register indirect with post-increment or
pre-decrement
31
0
• Register indirect with post-increment @ERn+
General register contents
op
r
• Register indirect with pre-decrement @−ERn
31
1, 2, or 4
0
General register contents
op
r
Operand Size
Byte
Word
Longword
1, 2, or 4
Offset
1
2
4
Effective Address (EA)
Operand is general register contents.
31 24 23
0
Don’t care
31 24 23
0
Don’t care
31 24 23
0
Don’t care
31 24 23
0
Don’t care
Rev. 7.00 Sep. 11, 2009 Page 46 of 566
REJ09B0211-0700