HD6417750RF240V Datasheet, PDF (326/606 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 12 Programmable Pulse Generator (PPG)
12.3.5 PPG Output Mode Register (PMR)
The PMR is an 8-bit readable/writable register that selects the pulse output mode of the PPG for
each group. If inverted output is selected, a low-level pulse is output when PODRH is 1 and a
high-level pulse is output when PODRH is 0. If non-overlapping operation is selected, PPG
updates its output values on compare match A or B of the TPU that becomes the output trigger.
For details, refer to section 12.4.5, Non-Overlapping Pulse Output.
Bit Bit Name
7 G3INV
6 G2INV
5, 4 —
3 G3NOV
2 G2NOV
1, 0 —
Initial Value R/W
1
R/W
1
R/W
All 1
R/W
0
R/W
0
R/W
All 0
R/W
Description
Group 3 Inversion
Selects direct output or inverted output for pulse
output group 3.
0: Inverted output
1: Direct output
Group 2 Inversion
Selects direct output or inverted output for pulse
output group 2.
0: Inverted output
1: Direct output
Reserved
Group 3 Non-Overlap
Selects normal or non-overlapping operation for
pulse output group 3.
0: Normal operation (output values updated at
compare match A in the selected TPU channel)
1: Non-overlapping operation (output values at
compare match A or B in the selected TPU
channel)
Group 2 Non-Overlap
Selects normal or non-overlapping operation for
pulse output group 2.
0: Normal operation (output values updated at
compare match A in the selected TPU channel)
1: Non-overlapping operation (output values at
compare match A or B in the selected TPU
channel)
Reserved
Rev. 7.00 Sep. 11, 2009 Page 290 of 566
REJ09B0211-0700