HD6417750RF240V Datasheet, PDF (320/606 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 12 Programmable Pulse Generator (PPG)
12.3.1 Next Data Enable Registers H, L (NDERH, NDERL)
NDERH and NDERL are an 8-bit readable/writable register that enables or disables pulse output
on a bit-by-bit basis. The corresponding DDR also needs to be set to 1 in order to enable pulse
output by the PPG.
NDERH
Bit Bit Name
7
NDER15
6
NDER14
5
NDER13
4
NDER12
3
NDER11
2
NDER10
1
NDER9
0
NDER8
Initial Value R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Description
Next Data Enable 8 to 15
When a bit is set to 1 for pulse output by NDRH,
the value in the corresponding NDRH bit is
transferred to the PODRH bit by the selected output
trigger. Values are not transferred from NDRH to
PODRH for cleared bits.
NDERL
Bit Bit Name
7
NDER7
6
NDER6
5
NDER5
4
NDER4
3
NDER3
2
NDER2
1
NDER1
0
NDER0
Initial Value R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Description
Next Data Enable 0 to 7
When a bit is set to 1 for pulse output by NDRL, the
value in the corresponding NDRL bit is transferred
to the PODRL bit by the selected output trigger.
Values are not transferred from NDRL to PODRL
for cleared bits.
Rev. 7.00 Sep. 11, 2009 Page 284 of 566
REJ09B0211-0700