HD6417750RF240V Datasheet, PDF (14/606 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

7.2 Bus Arbitration................................................................................................................... 101
7.2.1 Order of Priority of the Bus Masters..................................................................... 101
7.2.2 Bus Transfer Timing ............................................................................................. 101
Section 8 Data Transfer Controller (DTC) ........................................................103
8.1 Features .............................................................................................................................. 103
8.2 Register Configuration....................................................................................................... 105
8.2.1 DTC Mode Register A (MRA) ............................................................................. 106
8.2.2 DTC Mode Register B (MRB).............................................................................. 107
8.2.3 DTC Source Address Register (SAR)................................................................... 107
8.2.4 DTC Destination Address Register (DAR)........................................................... 107
8.2.5 DTC Transfer Count Register A (CRA) ............................................................... 107
8.2.6 DTC Transfer Count Register B (CRB)................................................................ 108
8.2.7 DTC Enable Registers (DTCER) .......................................................................... 108
8.2.8 DTC Vector Register (DTVECR)......................................................................... 109
8.3 Activation Sources ............................................................................................................. 109
8.4 Location of Register Information and DTC Vector Table ................................................. 110
8.5 Operation............................................................................................................................ 114
8.5.1 Normal Mode........................................................................................................ 115
8.5.2 Repeat Mode ......................................................................................................... 116
8.5.3 Block Transfer Mode ............................................................................................ 117
8.5.4 Chain Transfer ...................................................................................................... 119
8.5.5 Interrupts............................................................................................................... 120
8.5.6 Operation Timing.................................................................................................. 120
8.5.7 Number of DTC Execution States ........................................................................ 121
8.6 Procedures for Using DTC................................................................................................. 123
8.6.1 Activation by Interrupt.......................................................................................... 123
8.6.2 Activation by Software ......................................................................................... 123
8.7 Examples of Use of the DTC ............................................................................................. 123
8.7.1 Normal Mode........................................................................................................ 123
8.7.2 Chain Transfer ...................................................................................................... 124
8.7.3 Software Activation .............................................................................................. 125
8.8 Usage Notes ....................................................................................................................... 126
8.8.1 Module Stop Mode Setting ................................................................................... 126
8.8.2 On-Chip RAM ...................................................................................................... 126
8.8.3 DTCE Bit Setting.................................................................................................. 126
Section 9 I/O Ports.............................................................................................127
9.1 Port 1.................................................................................................................................. 130
9.1.1 Port 1 Data Direction Register (P1DDR).............................................................. 130
9.1.2 Port 1 Data Register (P1DR)................................................................................. 131
Rev. 7.00 Sep. 11, 2009 Page xii of xxxiv
REJ09B0211-0700