HD6417750RF240V Datasheet, PDF (126/606 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 6 PC Break Controller (PBC)
BARA
BCRA
Mask control
Comparator
Internal address
Control
logic
Match signal
Access
status
Comparator
Control
logic
Match signal
PC break
interrupt
Mask control
BARB
BCRB
Figure 6.1 Block Diagram of PC Break Controller
6.2 Register Descriptions
The PC break controller has the following registers. For details on register addresses and register
states during each process, refer to appendix A, On-Chip I/O Register.
• Break address register A (BARA)
• Break address register B (BARB)
• Break control register A (BCRA)
• Break control register B (BCRB)
6.2.1 Break Address Register A (BARA)
BARA is a 32-bit readable/writable register that specifies the channel A break address.
Bit
Bit Name
31 to 24 —
Initial Value R/W
Undefined —
23 to 0 BAA23 to BAA0 H'000000
R/W
Description
Reserved
These bits are read as an undefined value
and cannot be modified.
These bits set the channel A PC break
address.
Rev. 7.00 Sep. 11, 2009 Page 90 of 566
REJ09B0211-0700