HD6417750RF240V Datasheet, PDF (467/606 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 15 Controller Area Network (HCAN)
15.8.3 HCAN Sleep Mode
The bus operation interrupt flag (IRR12) in the interrupt register (IRR) is set by CAN bus
operation in HCAN sleep mode. Therefore, this flag is not used by the HCAN to indicate sleep
mode release. Note that the reset status bit (GSR3) in the general status register (GSR) is set in
sleep mode.
15.8.4 Interrupts
When the mailbox interrupt mask register (MBIMR) is set, the interrupt register (IRR8, 2, 1) is not
set by reception completion, transmission completion, or transmission cancellation for the set
mailboxes.
15.8.5 Error Counters
In the case of error active and error passive, REC and TEC normally count up and down. In the
bus-off state, 11-bit recessive sequences are counted (REC + 1) using REC. If REC reaches 96
during the count, IRR4 and GSR1 are set.
15.8.6 Register Access
Byte or word access can be used on all HCAN registers. Longword access cannot be used.
15.8.7 HCAN Medium-Speed Mode
In medium-speed mode, neither read nor write is possible for the HCAN registers.
15.8.8 Register Hold in Standby Modes
All HCAN registers are initialized in hardware standby mode and software standby mode.
15.8.9 Usage of Bit Manipulation Instructions
The HCAN status flags are cleared by writing 1, so do not use a bit manipulation instruction to
clear a flag.
When clearing a flag, use the MOV instruction to write 1 to only the bit that is to be cleared.
Rev. 7.00 Sep. 11, 2009 Page 431 of 566
REJ09B0211-0700