HD6417750RF240V Datasheet, PDF (422/606 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 15 Controller Area Network (HCAN)
• Local acceptance filter mask L (LAFML)
• Message control (8 bit × 8 registers × 16 sets) (MC0 to MC15)
• Message data (8 bit × 8 registers × 16 sets) (MD0 to MD15)
• HCAN Monitor Register (HCANMON)
15.3.1 Master Control Register (MCR)
The master control register (MCR) is an 8-bit register that controls the HCAN.
Bit Bit Name Initial Value R/W
7
MCR7
0
R/W
6
—
0
R
5
MCR5
0
R/W
4, 3 —
All 0
R
2
MCR2
0
R/W
1
MCR1
0
R/W
Description
HCAN Sleep Mode Release
When this bit is set to 1, the HCAN automatically
exits HCAN sleep mode on detection of CAN bus
operation.
Reserved
This bit is always read as 0. Only 0 should be written
to this bit.
HCAN Sleep Mode
When this bit is set to 1, the HCAN transits to HCAN
sleep mode. When this bit is cleared to 0, HCAN
sleep mode is released.
Reserved
These bits are always read as 0. Only 0 should be
written to these bits.
Message Transmission Method
0: Transmission order determined by message
identifier priority
1: Transmission order determined by mailbox (buffer)
number priority (TXPR1 > TXPR15)
Halt Request
When this bit is set to 1, the HCAN transits to HCAN
HALT mode. When this bit is cleared to 0, HCAN
HALT mode is released.
Rev. 7.00 Sep. 11, 2009 Page 386 of 566
REJ09B0211-0700