HD6417750RF240V Datasheet, PDF (374/606 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 14 Serial Communication Interface (SCI)
14.4 Operation in Asynchronous Mode
Figure 14.2 shows the general format for asynchronous serial communication. One frame consists
of a start bit (low level), followed by data (in LSB-first order), a parity bit (high or low level), and
finally stop bits (high level). In asynchronous serial communication, the transmission line is
usually held in the mark state (high level). The SCI monitors the transmission line. When the
transmission line goes to the space state (low level), the SCI recognizes a start bit and starts serial
communication. In asynchronous serial communication, the communication line is usually held in
the mark state (high level). The SCI monitors the communication line, and when it goes to the
space state (low level), recognizes a start bit and starts serial communication. Inside the SCI, the
transmitter and receiver are independent units, enabling full-duplex. Both the transmitter and the
receiver also have a double-buffered structure, so data can be read or written during transmission
or reception, enabling continuous data transfer.
1
LSB
MSB
Serial _{0 D0 D1 D2 D3 D4 D5 D6 D7 0/1 1}
1
data
Start
bit
Transmit/receive data
Parity Stop bit
bit
1 bit
7 or 8 bit
1 bit,
1 or
or none 2 bit
Idle state
(mark state)
1
One unit of transfer data (character or frame)
Figure 14.2 Data Format in Asynchronous Communication
(Example with 8-Bit Data, Parity, Two Stop Bits)
14.4.1 Data Transfer Format
Table 14.10 shows the data transfer formats that can be used in asynchronous mode. Any of 12
transfer formats can be selected according to the SMR setting. For details on the multiprocessor
bit, refer to section 14.5, Multiprocessor Communication Function.
Rev. 7.00 Sep. 11, 2009 Page 338 of 566
REJ09B0211-0700