HD6417750RF240V Datasheet, PDF (327/606 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 12 Programmable Pulse Generator (PPG)
12.4 Operation
12.4.1 Overview
Figure 12.2 shows a block diagram of the PPG. PPG pulse output is enabled when the
corresponding bits in P1DDR and NDER are set to 1. An initial output value is determined by its
corresponding PODR initial setting. When the compare match event specified by PCR occurs, the
corresponding NDR bit contents are transferred to PODR to update the output values.
The sequential output of up to 8 bits of data is possible by writing new output data to NDR before
the next compare match.
DDR
NDER
Q
Output trigger signal
Pulse output pin
C
Q PODR D
Q NDR D
Internal data bus
Normal output/inverted output
Figure 12.2 PPG Output Operation
Rev. 7.00 Sep. 11, 2009 Page 291 of 566
REJ09B0211-0700