HD6417750RF240V Datasheet, PDF (276/606 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 10 16-Bit Timer Pulse Unit (TPU)
10.9.9 Contention between TGR Write and Input Capture
If an input capture signal is generated in the T₂ state of a TGR write cycle, the input capture
operation takes precedence and the write to TGR is not performed.
Figure 10.50 shows the timing in this case.
φ
Address
TGR write cycle
T₁
T₂
TGR address
Write signal
Input capture
signal
TCNT
M
TGR
M
Figure 10.50 Contention between TGR Write and Input Capture
Rev. 7.00 Sep. 11, 2009 Page 240 of 566
REJ09B0211-0700