HD6417750RF240V Datasheet, PDF (475/606 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 16 A/D Converter
Table 16.2 Analog Input Channels and Corresponding ADDR Registers
Group 0
(CH2 = 0)
AN0
AN1
AN2
AN3
Analog Input Channel
CH3 = 0
Group 1
(CH2 = 1)
Group 2
(CH2 = 0)
AN4
AN8
AN5
AN9
AN6
AN10
AN7
AN11
CH3 = 1
—
(CH2 = 1)
Setting
prohibited
Setting
prohibited
Setting
prohibited
Setting
prohibited
A/D Data Register to
Be Stored the Results
of A/D Conversion
ADDRA
ADDRB
ADDRC
ADDRD
16.3.2 A/D Control/Status Register (ADCSR)
ADCSR controls A/D conversion operations.
Bit Bit Name Initial Value R/W Description
7
ADF
0
R/(W)
A/D End Flag
A status flag that indicates the end of A/D
conversion.
[Setting conditions]
• When A/D conversion ends
• When A/D conversion ends on all specified
channels
[Clearing conditions]
• When 0 is written after reading ADF = 1
• When the DTC is activated by an ADI interrupt
and ADDR is read
6
ADIE
0
R/W A/D Interrupt Enable
A/D conversion end interrupt (ADI) request enabled
when 1 is set
Rev. 7.00 Sep. 11, 2009 Page 439 of 566
REJ09B0211-0700