HD6417750RF240V Datasheet, PDF (26/606 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Figure 10.17 Cascaded Operation Setting Procedure .................................................................. 209
Figure 10.18 Example of Cascaded Operation (1)....................................................................... 210
Figure 10.19 Example of Cascaded Operation (2)....................................................................... 210
Figure 10.20 Example of PWM Mode Setting Procedure ........................................................... 213
Figure 10.21 Example of PWM Mode Operation (1) .................................................................. 214
Figure 10.22 Example of PWM Mode Operation (2) .................................................................. 214
Figure 10.23 Example of PWM Mode Operation (3) .................................................................. 215
Figure 10.24 Example of Phase Counting Mode Setting Procedure............................................ 217
Figure 10.25 Example of Phase Counting Mode 1 Operation ..................................................... 217
Figure 10.26 Example of Phase Counting Mode 2 Operation ..................................................... 218
Figure 10.27 Example of Phase Counting Mode 3 Operation ..................................................... 219
Figure 10.28 Example of Phase Counting Mode 4 Operation ..................................................... 220
Figure 10.29 Phase Counting Mode Application Example.......................................................... 222
Figure 10.30 Count Timing in Internal Clock Operation ............................................................ 226
Figure 10.31 Count Timing in External Clock Operation ........................................................... 226
Figure 10.32 Output Compare Output Timing ............................................................................ 227
Figure 10.33 Input Capture Input Signal Timing......................................................................... 227
Figure 10.34 Counter Clear Timing (Compare Match) ............................................................... 228
Figure 10.35 Counter Clear Timing (Input Capture) ................................................................... 228
Figure 10.36 Buffer Operation Timing (Compare Match) .......................................................... 229
Figure 10.37 Buffer Operation Timing (Input Capture) .............................................................. 229
Figure 10.38 TGI Interrupt Timing (Compare Match) ................................................................ 230
Figure 10.39 TGI Interrupt Timing (Input Capture).................................................................... 230
Figure 10.40 TCIV Interrupt Setting Timing............................................................................... 231
Figure 10.41 TCIU Interrupt Setting Timing............................................................................... 232
Figure 10.42 Timing for Status Flag Clearing by CPU ............................................................... 232
Figure 10.43 Timing for Status Flag Clearing by DTC Activation ............................................. 233
Figure 10.44 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode ................. 234
Figure 10.45 Contention between TCNT Write and Clear Operations........................................ 235
Figure 10.46 Contention between TCNT Write and Increment Operations ................................ 236
Figure 10.47 Contention between TGR Write and Compare Match ........................................... 237
Figure 10.48 Contention between Buffer Register Write and Compare Match........................... 238
Figure 10.49 Contention between TGR Read and Input Capture ................................................ 239
Figure 10.50 Contention between TGR Write and Input Capture ............................................... 240
Figure 10.51 Contention between Buffer Register Write and Input Capture............................... 241
Figure 10.52 Contention between Overflow and Counter Clearing ............................................ 242
Figure 10.53 Contention between TCNT Write and Overflow ................................................... 243
Section 11 Motor Management Timer (MMT)
Figure 11.1 Block Diagram of MMT ........................................................................................ 246
Figure 11.2 Sample Operating Mode Setting Procedure ........................................................... 254
Rev. 7.00 Sep. 11, 2009 Page xxiv of xxxiv
REJ09B0211-0700