HD6417750RF240V Datasheet, PDF (278/606 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 10 16-Bit Timer Pulse Unit (TPU)
10.9.11 Contention between Overflow/Underflow and Counter Clearing
If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is
not set and TCNT clearing takes precedence.
Figure 10.52 shows the operation timing when a TGR compare match is specified as the clearing
source, and when H'FFFF is set in TGR.
φ
TCNT input
clock
TCNT
Counter
clear signal
TGF
TCFV
H'FFFF
Prohibited
H'0000
Figure 10.52 Contention between Overflow and Counter Clearing
Rev. 7.00 Sep. 11, 2009 Page 242 of 566
REJ09B0211-0700