HD6417750RF240V Datasheet, PDF (313/606 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Bit Bit Name Initial Value R/W
7
POE3M1 0
R/W
6
POE3M0 0
R/W
5
POE2M1 0
R/W
4
POE2M0 0
R/W
3
POE1M1 0
R/W
2
POE1M0 0
R/W
Section 11 Motor Management Timer (MMT)
Description
POE3 Modes 1 and 0
These bits select the input mode of the POE3 pin.
00: Request accepted at falling edge of POE3 input
01: POE3 input is sampled for low level 16 times
every φ/8 clock, and request is accepted when
all samples are low level
10: POE3 input is sampled for low level 16 times
every φ/16 clock, and request is accepted when
all samples are low level
11: POE3 input is sampled for low level 16 times
every φ/128 clock, and request is accepted
when all samples are low level
POE2 Modes 1 and 0
These bits select the input mode of the POE2 pin.
00: Request accepted at falling edge of POE2 input
01: POE2 input is sampled for low level 16 times
every φ/8 clock, and request is accepted when
all samples are low level
10: POE2 input is sampled for low level 16 times
every φ/16 clock, and request is accepted when
all samples are low level
11: POE2 input is sampled for low level 16 times
every φ/128 clock, and request is accepted
when all samples are low level
POE1 Modes 1 and 0
These bits select the input mode of the POE1 pin.
00: Request accepted at falling edge of POE1 input
01: POE1 input is sampled for low level 16 times
every φ/8 clock, and request is accepted when
all samples are low level
10: POE1 input is sampled for low level 16 times
every φ/16 clock, and request is accepted when
all samples are low level
11: POE1 input is sampled for low level 16 times
every φ/128 clock, and request is accepted
when all samples are low level
Rev. 7.00 Sep. 11, 2009 Page 277 of 566
REJ09B0211-0700