HD6417750RF240V Datasheet, PDF (479/606 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 16 A/D Converter
16.4.3 Input Sampling and A/D Conversion Time
The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog
input when the A/D conversion start delay time (t_D) has passed after the ADST bit is set to 1, then
starts conversion. Figure 16.2 shows the A/D conversion timing. Table 16.3 shows the A/D
conversion time.
As indicated in figure 16.2, the A/D conversion time (t_CONV) includes t_D and the input sampling time
(t_SPL). The length of t_D varies depending on the timing of the write access to ADCSR. The total
conversion time therefore varies within the ranges indicated in table 16.3.
In scan mode, the values given in table 16.3 apply to the first conversion time. The values given in
table 16.4 apply to the second and subsequent conversions. In both cases, set bits CKS1 and CKS0
in ADCR to give an A/D conversion time within the range shown in table 21.7.
(1)
φ
Address
(2)
Write signal
Input sampling
timing
ADF
t_D
t_SPL
Legend:
(1): ADCSR write cycle
(2) ADCSR address
t_D: A/D conversion start delay
t_SPL: Input sampling time
t_CONV: A/D conversion time
t_CONV
Figure 16.2 A/D Conversion Timing
Rev. 7.00 Sep. 11, 2009 Page 443 of 566
REJ09B0211-0700