HD6417750RF240V Datasheet, PDF (307/606 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 11 Motor Management Timer (MMT)
Contention between Compare Register Write and Compare Match: If a compare match
occurs in the T₃ state of a compare register (TGR or TPDR) write cycle, the compare register write
is not performed, and data is transferred from the buffer register (TBRU, TBRV, TBRW, or
TPBR) to the compare register by a buffer operation.
Figure 11.18 shows the timing in this case.
φ
Address
Compare register
write cycle
T₁
T₂
T₃
Compare register address
Write signal
Compare match
signal
TGI interrupt
Buffer register
N
Compare register
N
Compare register
write data
Figure 11.18 Contention between Compare Register Write and Compare Match
Rev. 7.00 Sep. 11, 2009 Page 271 of 566
REJ09B0211-0700