HD6417750RF240V Datasheet, PDF (76/606 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 2 CPU
Table 2.10 Block Data Transfer Instructions
Instruction
EEPMOV.B
Size
—
EEPMOV.W —
Function
if R4L ≠ 0 then
Repeat @ER5+ → @ER6+
R4L–1 → R4L
Until R4L = 0
else next;
if R4 ≠ 0 then
Repeat @ER5+ → @ER6+
R4–1 → R4
Until R4 = 0
else next;
Transfers a data block. Starting from the address set in ER5, transfers
data for the number of bytes set in R4L or R4 to the address location set
in ER6.
Execution of the next instruction begins as soon as the transfer is
completed.
2.6.2 Basic Instruction Formats
This LSI instructions consist of 2-byte (1-word) units. An instruction consists of an operation field
(op field), a register field (r field), an effective address extension (EA field), and a condition field
(cc).
Figure 2.11 shows examples of instruction formats.
Rev. 7.00 Sep. 11, 2009 Page 40 of 566
REJ09B0211-0700