HD6417750RF240V Datasheet, PDF (537/606 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 20 Power-Down Modes
20.7 φ Clock Output Disabling Function
The output of the φ clock can be controlled by means of the PSTOP bit in SCKCR, and DDR for
the corresponding port. When the PSTOP bit is set to 1, the φ clock stops at the end of the bus
cycle, and φ output goes high. φ clock output is enabled when the PSTOP bit is cleared to 0. When
DDR for the corresponding port is cleared to 0, φ clock output is disabled and input port mode is
set. Table 20.4 shows the state of the φ pin in each processing state.
Table 20.4 φ Pin State in Each Processing State
Register Settings
DDR
PSTOP
0
X
1
0
1
1
Legend:
X: Don’t care
Normal Mode
High impedance
φ output
Fixed high
Sleep Mode
High impedance
φ output
Fixed high
Software
Standby Mode
High impedance
Fixed high
Fixed high
Hardware
Standby Mode
High impedance
High impedance
High impedance
Rev. 7.00 Sep. 11, 2009 Page 501 of 566
REJ09B0211-0700