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HD6417750RF240V Datasheet, PDF (75/606 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series | |||
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Section 2 CPU
Table 2.9 System Control Instructions
Instruction Size* Function
TRAPA
â
Starts trap-instruction exception handling.
RTE
â
Returns from an exception-handling routine.
SLEEP
â
Causes a transition to a power-down state.
LDC
B/W (EAs) â CCR, (EAs) â EXR
Moves the source operand contents or immediate data to CCR or EXR.
Although CCR and EXR are 8-bit registers, word-size transfers are
performed between them and memory. The upper 8 bits are valid.
STC
B/W CCR â (EAd), EXR â (EAd)
Transfers CCR or EXR contents to a general register or memory.
Although CCR and EXR are 8-bit registers, word-size transfers are
performed between them and memory. The upper 8 bits are valid.
ANDC
B
CCR ⧠#IMM â CCR, EXR ⧠#IMM â EXR
Logically ANDs the CCR or EXR contents with immediate data.
ORC
B
CCR ⨠#IMM â CCR, EXR ⨠#IMM â EXR
Logically ORs the CCR or EXR contents with immediate data.
XORC
B
CCR â #IMM â CCR, EXR â #IMM â EXR
Logically XORs the CCR or EXR contents with immediate data.
NOP
â
PC + 2 â PC
Only increments the program counter.
Note: * Refers to the operand size.
B: Byte
W: Word
L: Longword
Rev. 7.00 Sep. 11, 2009 Page 39 of 566
REJ09B0211-0700
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