HD6417750RF240V Datasheet, PDF (127/606 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 6 PC Break Controller (PBC)
6.2.2 Break Address Register B (BARB)
BARB is the channel B break address register. The bit configuration is the same as for BARA.
6.2.3 Break Control Register A (BCRA)
BCRA controls channel A PC breaks. BCRA also contains a condition match flag.
Bit Bit Name Initial Value R/W Description
7 CMFA
0
R/W Condition Match Flag A
[Setting condition]
• When a condition set for channel A is satisfied
[Clearing condition]
• When 0 is written to CMFA after reading CMFA = 1
6 CDA
0
R/W CPU Cycle/DTC Cycle Select A
Selects the channel A break condition bus master.
0: CPU
1: CPU or DTC
5 BAMRA2 0
4 BAMRA1 0
3 BAMRA0 0
R/W Break Address Mask Register A2 to A0
R/W _{These bits specify which bits of the break address set in}
R/W _{BARA are to be masked.}
000: BAA23 to 0 (All bits are unmasked)
001: BAA23 to 1 (Lowest bit is masked)
010: BAA23 to 2 (Lower 2 bits are masked)
011: BAA23 to 3 (Lower 3 bits are masked)
100: BAA23 to 4 (Lower 4 bits are masked)
101: BAA23 to 8 (Lower 8 bits are masked)
110: BAA23 to 12 (Lower 12 bits are masked)
111: BAA23 to 16 (Lower 16 bits are masked)
2 CSELA1 0
1 CSELA0 0
R/W Break Condition Select A
R/W _{Selects break condition of channel A.}
00: Instruction fetch is used as break condition
01: Data read cycle is used as break condition
10: Data write cycle is used as break condition
11: Data read/write cycle is used as break condition
0 BIEA
0
R/W Break Interrupt Enable A
When this bit is 1, the PC break interrupt request of
channel A is enabled.
Rev. 7.00 Sep. 11, 2009 Page 91 of 566
REJ09B0211-0700