HD6417750RF240V Datasheet, PDF (110/606 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 5 Interrupt Controller
5.3.4 IRQ Status Register (ISR)
ISR is an 8-bit readable/writable register that indicates the status of IRQ0 to IRQ5 interrupt
requests.
Bit Bit Name Initial Value R/W Description
7, 6 −
All 0
R/W Reserved
Only 0 should be written to these bits.
5
IRQ5F
0
4
IRQ4F
0
3
IRQ3F
0
2
IRQ2F
0
1
IRQ1F
0
0
IRQ0F
0
R/W [Setting condition]
R/W _{• When the interrupt source selected by the ISCR}
R/W
R/W
registers occurs
R/W ^{[Clearing conditions]}
R/W _{• Cleared by reading IRQnF flag when IRQnF = 1,}
then writing 0 to IRQnF flag
• When interrupt exception handling is executed
when low-level detection is set and IRQn input is
high
• When IRQn interrupt exception handling is
executed when falling, rising, or both-edge
detection is set
• When the DTC is activated by an IRQn interrupt,
and the DISEL bit in MRB of the DTC is cleared
to 0
(n = 5 to 0)
Rev. 7.00 Sep. 11, 2009 Page 74 of 566
REJ09B0211-0700