HD6417750RF240V Datasheet, PDF (125/606 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 6 PC Break Controller (PBC)
Section 6 PC Break Controller (PBC)
The PC break controller (PBC) provides functions that simplify program debugging. Using these
functions, it is easy to create a self-monitoring debugger, enabling programs to be debugged with
the chip alone, without using an in-circuit emulator. A block diagram of the PC break controller is
shown in figure 6.1.
Note: No PBC is implemented in the H8S/2614 and H8S/2616.
6.1 Features
• Two break channels (A and B)
• 24-bit break address
⎯ Bit masking possible
• Four types of break compare conditions
⎯ Instruction fetch
⎯ Data read
⎯ Data write
⎯ Data read/write
• Bus master
⎯ Either CPU or CPU/DTC can be selected
• The timing of PC break exception handling after the occurrence of a break condition is as
follows:
⎯ Immediately before execution of the instruction fetched at the set address (instruction
fetch)
⎯ Immediately after execution of the instruction that accesses data at the set address (data
access)
• Module stop mode can be set
Rev. 7.00 Sep. 11, 2009 Page 89 of 566
REJ09B0211-0700