HD6417750RF240V Datasheet, PDF (498/606 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 18 ROM
18.5.4 Erase Block Register 2 (EBR2)
EBR2 specifies the flash memory erase area block. EBR2 is initialized to H'00 when the SWE bit
in FLMCR1 is 0. Do not set more than one bit at a time, as this will cause all the bits in EBR2 to
be automatically cleared to 0.
Bit Bit Name
7 to —
2
1
EB9
0
EB8
Initial Value R/W
All 0
—
0
R/W
0
R/W
Description
Reserved
These bits are always read as 0.
When this bit is set to 1, 32 kbytes of EB9
(H'018000 to H'01FFFF) will be erased.
When this bit is set to 1, 32 kbytes of EB8
(H'010000 to H'017FFF) will be erased.
18.5.5 RAM Emulation Register (RAMER)
RAMER specifies the area of flash memory to be overlapped with part of RAM when emulating
real-time flash memory programming. RAMER settings should be made in user mode or user
program mode. To ensure correct operation of the emulation function, the ROM for which RAM
emulation is performed should not be accessed immediately after this register has been modified.
Normal execution of an access immediately after register modification is not guaranteed.
Bit Bit Name
7, 6 —
5, 4 —
3
RAMS
Initial Value R/W
All 0
—
All 0
R/W
0
R/W
Description
Reserved
These bits are always read as 0.
Reserved
Only 0 should be written to these bits.
RAM Select
Specifies selection or non-selection of flash
memory emulation in RAM. When RAMS = 1, the
flash memory is overlapped with part of RAM, and
all flash memory block are program/erase-
protected.
Rev. 7.00 Sep. 11, 2009 Page 462 of 566
REJ09B0211-0700