HD6417750RF240V Datasheet, PDF (273/606 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 10 16-Bit Timer Pulse Unit (TPU)
10.9.6 Contention between TGR Write and Compare Match
If a compare match occurs in the T₂ state of a TGR write cycle, the TGR write takes precedence
and the compare match signal is inhibited. A compare match does not occur even if the previous
value is written.
Figure 10.47 shows the timing in this case.
TGR write cycle
T₁
T₂
φ
Address
TGR address
Write signal
Compare
match signal
TCNT
Prohibited
N
N+1
TGR
N
M
TGR write data
Figure 10.47 Contention between TGR Write and Compare Match
Rev. 7.00 Sep. 11, 2009 Page 237 of 566
REJ09B0211-0700