HD6417750RF240V Datasheet, PDF (530/606 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 20 Power-Down Modes
When the RES pin is set low and medium-speed mode is cancelled, operation shifts to the reset
state. The same applies in the case of a reset caused by overflow of the watchdog timer.
When the STBY pin is driven low, a transition is made to hardware standby mode.
Figure 20.2 shows the timing for transition to and clearance of medium-speed mode.
φ,
supporting module clock
Medium-speed mode
Bus master clock
Internal address bus
SCKCR
SCKCR
Internal write signal
Figure 20.2 Medium-Speed Mode Transition and Clearance Timing
Rev. 7.00 Sep. 11, 2009 Page 494 of 566
REJ09B0211-0700