HD6417750RF240V Datasheet, PDF (514/606 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 19 Clock Pulse Generator
19.1 Register Descriptions
The on-chip clock pulse generator has the following registers. For details on register addresses,
refer to appendix A, On-Chip I/O Register.
• System clock control register (SCKCR)
• Low-power control register (LPWRCR)
19.1.1 System Clock Control Register (SCKCR)
SCKCR performs φ clock output control, selection of operation when the PLL circuit frequency
multiplication factor is changed, and medium-speed mode control.
Bit Bit Name
7
PSTOP
6 to —
4
Initial Value R/W
0
R/W
All 0
—
Description
φ Clock Output Disable
Controls φ output.
High-speed Mode, Medium-Speed Mode
0: φ output
1: Fixed high
Sleep Mode
0: φ output
1: Fixed high
Software Standby Mode
0: Fixed high
1: Fixed high
Hardware Standby Mode
0: High impedance
1: High impedance
Reserved
These bits are always read as 0.
Rev. 7.00 Sep. 11, 2009 Page 478 of 566
REJ09B0211-0700