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HD6417750RF240V Datasheet, PDF (70/606 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series | |||
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Section 2 CPU
Instruction Size*1 Function
DIVXS
B/W
Rd ÷ Rs â Rd
Performs signed division on data in two general registers: either 16 bits ÷
8 bits â 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits â 16-bit
quotient and 16-bit remainder.
CMP
B/W/L
Rd â Rs, Rd â #IMM
Compares data in a general register with data in another general register
or with immediate data, and sets CCR bits according to the result.
NEG
B/W/L
0 â Rd â Rd
Takes the two's complement (arithmetic complement) of data in a general
register.
EXTU
W/L
Rd (zero extension) â Rd
Extends the lower 8 bits of a 16-bit register to word size, or the lower 16
bits of a 32-bit register to longword size, by padding with zeros on the
left.
EXTS
W/L
Rd (sign extension) â Rd
Extends the lower 8 bits of a 16-bit register to word size, or the lower 16
bits of a 32-bit register to longword size, by extending the sign bit.
TAS*2
B
@ERd â 0, 1 â (<bit 7> of @ERd)
Tests memory contents, and sets the most significant bit (bit 7) to 1.
MAC
â
(EAs) Ã (EAd) + MAC â MAC
Performs signed multiplication on memory contents and adds the result
to the multiply-accumulate register. The following operations can be
performed:
16 bits à 16 bits + 32 bits â 32 bits, saturating
16 bits à 16 bits + 42 bits â 42 bits, non-saturating
CLRMAC
â
0 â MAC
Clears the multiply-accumulate register to zero.
LDMAC
L
STMAC
Rs â MAC, MAC â Rd
Transfers data between a general register and a multiply-accumulate
register.
Notes: 1. Refers to the operand size.
B: Byte
W: Word
L: Longword
2. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.
Rev. 7.00 Sep. 11, 2009 Page 34 of 566
REJ09B0211-0700
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