HD6417750RF240V Datasheet, PDF (347/606 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 13 Watchdog Timer
13.5.3 Changing Value of CKS2 to CKS0
If bits CKS0 to CKS2 in TCSR are written to while the WDT is operating, errors could occur in
the incrementation. Software must be used to stop the watchdog timer (by clearing the TME bit to
0) before changing the value of bits CKS0 to CKS2.
13.5.4 Switching between Watchdog Timer Mode and Interval Timer Mode
If the mode is switched from watchdog timer to interval timer while the WDT is operating, errors
could occur in the incrementation. Software must be used to stop the watchdog timer (by clearing
the TME bit to 0) before switching the mode.
13.5.5 Internal Reset in Watchdog Timer Mode
This LSI is not reset internally if TCNT overflows while the RSTE bit is cleared to 0 during
watchdog timer operation, however TCNT and TCSR of the WDT are reset.
TCNT, TCSR, or RSTCR cannot be written to for 132 states following an overflow. During this
period, any attempt to read the WOVF flag is not acknowledged. Accordingly, wait 132 states
after overflow to write 0 to the WOVF flag for clearing.
13.5.6 OVF Flag Clearing in Intervel Timer Mode
When the OVF flag setting conflicts with the OVF flag reading in interval timer mode, writing 0
to the OVF bit may not clear the flag even though the OVF bit has been read while it is 1. If there
is a possibility that the OVF flag setting and reading will conflict, such as when the OVF flag is
polled with the intervel timer interrupt disabled, read the OVF bit while it is 1 at least twice before
writing 0 to the OVF bit to clear the flag.
Rev. 7.00 Sep. 11, 2009 Page 311 of 566
REJ09B0211-0700