HD6417750RF240V Datasheet, PDF (474/606 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 16 A/D Converter
16.3 Register Description
The A/D converter has the following registers. For details on register addresses, refer to appendix
A, On-Chip I/O Register. The MSTPA1 bit in the module stop control register (MSTPCRA)
specifies the modes of this module as module stop mode. For details on the module stop control
register A (MSTPCRA), refer to section 20.1.2, Module Stop Control Register A to C (MSTPCRA
to MSTPCRC).
• A/D data register A (ADDRA)
• A/D data register B (ADDRB)
• A/D data register C (ADDRC)
• A/D data register D (ADDRD)
• A/D control/status register (ADCSR)
• A/D control register (ADCR)
16.3.1 A/D Data Registers A to D (ADDRA to ADDRD)
There are four 16-bit read-only ADDR registers; ADDRA to ADDRD, used to store the results of
A/D conversion. The ADDR registers, which store a conversion result for each channel, are shown
in table 16.2.
The converted 10-bit data is stored in bits 6 to 15. The lower 6 bits are always read as 0.
The data bus between the CPU and the A/D converter is 8 bits wide. The upper byte can be read
directly from the CPU, however the lower byte should be read via a temporary register. The
temporary register contents are transferred from the ADDR when the upper byte data is read.
When reading the ADDR, read the upper byte before the lower byte, or read in word unit. When
only the lower byte is read, the contents are not guaranteed.
Rev. 7.00 Sep. 11, 2009 Page 438 of 566
REJ09B0211-0700