HD6417750RF240V Datasheet, PDF (346/606 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 13 Watchdog Timer
TCNT write
Writing to RSTE and RSTS bits
Address:
15
H'FF74
H'FF76
H'5A
87
0
Write data
TCSR write
Writing 0 to WOVF bit
15
Address: H'FF74
H'FF76
H'A5
87
0
Write data or H'00
Figure 13.2 Writing to TCNT, TCSR, and RSTCSR (Example for WDT0)
Reading TCNT, TCSR, and RSTCSR (WDT0)
These registers are read in the same way as other registers. The read addresses are H'FF74 for
TCSR, H'FF75 for TCNT, and H'FF77 for RSTCSR.
13.5.2 Contention between Timer Counter (TCNT) Write and Increment
If a timer counter clock pulse is generated during the T₂ state of a TCNT write cycle, the write
takes priority and the timer counter is not incremented. Figure 13.3 shows this operation.
TCNT write cycle
T1
T2
φ
Address
Internal write signal
TCNT input clock
TCNT
N
M
Counter write data
Figure 13.3 Contention between TCNT Write and Increment
Rev. 7.00 Sep. 11, 2009 Page 310 of 566
REJ09B0211-0700