HD6417750RF240V Datasheet, PDF (245/606 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 10 16-Bit Timer Pulse Unit (TPU)
10.4.4 Cascaded Operation
In cascaded operation, two 16-bit counters for different channels are used together as a 32-bit
counter.
This function works by counting the channel 1 (channel 4) counter clock upon overflow/underflow
of TCNT_2 (TCNT_5) as set in bits TPSC0 to TPSC2 in TCR.
Underflow occurs only when the lower 16-bit TCNT is in phase-counting mode.
Table 10.29 shows the register combinations used in cascaded operation.
Note: When phase counting mode is set for channel 1 or 4, the counter clock setting is invalid
and the counters operates independently in phase counting mode.
Table 10.29 Cascaded Combinations
Combination
Channels 1 and 2
Channels 4 and 5
Upper 16 Bits
TCNT_1
TCNT_4
Lower 16 Bits
TCNT_2
TCNT_5
Example of Cascaded Operation Setting Procedure: Figure 10.17 shows an example of the
setting procedure for cascaded operation.
Cascaded operation
Set cascading
[1] Set bits TPSC2 to TPSC0 in the channel 1
(channel 4) TCR to B'1111 to select TCNT_2
(TCNT_5) overflow/underflow counting.
[2] Set the CST bit in TSTR for the upper and lower
[1]
channel to 1 to start the count operation.
Start count
[2]
<Cascaded operation>
Figure 10.17 Cascaded Operation Setting Procedure
Rev. 7.00 Sep. 11, 2009 Page 209 of 566
REJ09B0211-0700