HD6417750RF240V Datasheet, PDF (322/606 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 12 Programmable Pulse Generator (PPG)
12.3.3 Next Data Registers H, L (NDRH, NDRL)
NDRH and NDRL are an 8-bit readable/writable register that stores the data for the next pulse
output. The NDR addresses differ depending on whether pulse output groups have the same output
trigger or different output triggers.
NDRH
If pulse output groups 2 and 3 have the same output trigger, all eight bits are mapped to the same
address and can be accessed at one time, as shown below.
Bit Bit Name
7
NDR15
6
NDR14
5
NDR13
4
NDR12
3
NDR11
2
NDR10
1
NDR9
0
NDR8
Initial Value R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Description
Next Data Register 8 to 15
The register contents are transferred to the
corresponding PODRH bits by the output trigger
specified with PCR.
If pulse output groups 2 and output pulse groups 3 have different output triggers, the upper 4 bits
and the lower 4 bits are mapped to different addresses, as shown below.
Bit Bit Name
7
NDR15
6
NDR14
5
NDR13
4
NDR12
3 to —
0
Initial Value R/W
0
R/W
0
R/W
0
R/W
0
R/W
All 1
—
Description
Next Data Register 12 to 15
The register contents are transferred to the
corresponding PODRH bits by the output trigger
specified with PCR.
Reserved
These bits are always read as 1 and cannot be
modified.
Rev. 7.00 Sep. 11, 2009 Page 286 of 566
REJ09B0211-0700