HD6417750RF240V Datasheet, PDF (128/606 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 6 PC Break Controller (PBC)
6.2.4 Break Control Register B (BCRB)
BCRB is the channel B break control register. The bit configuration is the same as for BCRA.
6.3 Operation
The operation flow from break condition setting to PC break interrupt exception handling is
shown in section 6.3.1, PC Break Interrupt Due to Instruction Fetch, and 6.3.2, PC Break Interrupt
Due to Data Access, taking the example of channel A.
6.3.1 PC Break Interrupt Due to Instruction Fetch
1. Set the break address in BARA.
For a PC break caused by an instruction fetch, set the address of the first instruction byte as the
break address.
2. Set the break conditions in BCR.
Set bit 6 (CDA) to 0 to select the CPU because the bus master must be the CPU for a PC break
caused by an instruction fetch. Set the address bits to be masked to bits 3 to 5 (BAMA2 to
BAMA0). Set bits 1 and 2 (CSELA1 and CSELA0) to 00 to specify an instruction fetch as the
break condition. Set bit 0 (BIEA) to 1 to enable break interrupts.
3. When the instruction at the set address is fetched, a PC break request is generated immediately
before execution of the fetched instruction, and the condition match flag (CMFA) is set.
4. After priority determination by the interrupt controller, PC break interrupt exception handling
is started.
6.3.2 PC Break Interrupt Due to Data Access
1. Set the break address in BARA.
For a PC break caused by a data access, set the target ROM, RAM, I/O, or external address
space address as the break address. Stack operations and branch address reads are included in
data accesses.
2. Set the break conditions in BCRA.
Select the bus master with bit 6 (CDA). Set the address bits to be masked to bits 3 to 5
(BAMA2 to BAMA0). Set bits 1 and 2 (CSELA1 and CSELA0) to 01, 10, or 11 to specify
data access as the break condition. Set bit 0 (BIEA) to 1 to enable break interrupts.
3. After execution of the instruction that performs a data access on the set address, a PC break
request is generated and the condition match flag (CMFA) is set.
4. After priority determination by the interrupt controller, PC break interrupt exception handling
is started.
Rev. 7.00 Sep. 11, 2009 Page 92 of 566
REJ09B0211-0700