HD6417750RF240V Datasheet, PDF (85/606 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 2 CPU
Reset state*
RES ^{= High}
Exception handling state
Request for
exception
handling
End of
exception
handling
Program execution state
reInqtueerrsutpt
rBequusest
Enrdeoqfubeusts
SLEEP instruction
Bus-released state
Bus
request
End of
bus request
Program halt state
Notes: From any state, a transition to hardware standby mode occurs when STBY goes low.
* From any state except hardware standby mode, a transition to the reset state
occurs whenever RES goes low. A transition can also be made to the reset state
when the watchdog timer overflows.
Figure 2.13 State Transitions
2.9 Usage Notes
2.9.1 Usage Notes on Bit Manipulation Instructions
The BSET, BCLR, BNOT, BST, and BIST instructions are used to read data in bytes, then, after
bit manipulation, they write data in bytes again. Therefore, special care is necessary to use these
instructions for the registers and the ports that include write-only bit.
The BCLR instruction can be used to clear the flags in the internal I/O registers to 0. In this time,
if it is obvious that the flag has been set to 1 in the interrupt processing routine or other
processing, there is no need to read the flag beforehand.
Rev. 7.00 Sep. 11, 2009 Page 49 of 566
REJ09B0211-0700