HD6417750RF240V Datasheet, PDF (12/606 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

2.8 Processing States.................................................................................................................. 48
2.9 Usage Notes ......................................................................................................................... 49
2.9.1 Usage Notes on Bit Manipulation Instructions ....................................................... 49
Section 3 MCU Operating Modes .......................................................................51
3.1 Operating Mode Selection ................................................................................................... 51
3.2 Register Descriptions ........................................................................................................... 51
3.2.1 Mode Control Register (MDCR) ............................................................................ 52
3.2.2 System Control Register (SYSCR) ......................................................................... 53
3.3 Pin Functions in Each Operating Mode ............................................................................... 54
3.3.1 Pin Functions .......................................................................................................... 54
3.4 Address Map ........................................................................................................................ 55
Section 4 Exception Handling .............................................................................57
4.1 Exception Handling Types and Priority ............................................................................... 57
4.2 Exception Sources and Exception Vector Table .................................................................. 57
4.3 Reset..................................................................................................................................... 59
4.3.1 Reset Exception Handling....................................................................................... 59
4.3.2 Interrupts after Reset............................................................................................... 61
4.3.3 State of On-Chip Supporting Modules after Reset Release .................................... 61
4.4 Traces................................................................................................................................... 62
4.5 Interrupts .............................................................................................................................. 62
4.6 Trap Instruction.................................................................................................................... 63
4.7 Stack Status after Exception Handling................................................................................. 64
4.8 Usage Note........................................................................................................................... 65
Section 5 Interrupt Controller..............................................................................67
5.1 Features ................................................................................................................................ 67
5.2 Input/Output Pins ................................................................................................................. 69
5.3 Register Descriptions ........................................................................................................... 69
5.3.1 Interrupt Priority Registers A to H, J, K, M
(IPRA to IPRH,IPRJ, IPRK, IPRM) ....................................................................... 70
5.3.2 IRQ Enable Register (IER) ..................................................................................... 71
5.3.3 IRQ Sense Control Registers H and L (ISCRH, ISCRL)........................................ 71
5.3.4 IRQ Status Register (ISR)....................................................................................... 74
5.4 Interrupt ............................................................................................................................... 75
5.4.1 External Interrupts .................................................................................................. 75
5.4.2 Internal Interrupts.................................................................................................... 76
5.5 Interrupt Exception Handling Vector Table......................................................................... 76
5.6 Interrupt Control Modes and Interrupt Operation ................................................................ 79
5.6.1 Interrupt Control Mode 0 ........................................................................................ 79
Rev. 7.00 Sep. 11, 2009 Page x of xxxiv
REJ09B0211-0700