HD6417750RF240V Datasheet, PDF (22/606 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

18.5.2 Flash Memory Control Register 2 (FLMCR2)...................................................... 461
18.5.3 Erase Block Register 1 (EBR1) ............................................................................ 461
18.5.4 Erase Block Register 2 (EBR2) ............................................................................ 462
18.5.5 RAM Emulation Register (RAMER).................................................................... 462
18.6 On-Board Programming Modes......................................................................................... 463
18.6.1 Boot Mode ............................................................................................................ 464
18.6.2 Programming/Erasing in User Program Mode...................................................... 466
18.7 Flash Memory Emulation in RAM .................................................................................... 468
18.8 Flash Memory Programming/Erasing ................................................................................ 470
18.8.1 Program/Program-Verify ...................................................................................... 470
18.8.2 Erase/Erase-Verify................................................................................................ 472
18.8.3 Interrupt Handling when Programming/Erasing Flash Memory........................... 472
18.9 Program/Erase Protection .................................................................................................. 474
18.9.1 Hardware Protection ............................................................................................. 474
18.9.2 Software Protection............................................................................................... 474
18.9.3 Error Protection..................................................................................................... 474
18.10 Programmer Mode ............................................................................................................. 475
18.11 Power-Down States for Flash Memory.............................................................................. 475
18.12 Note on Switching from F-ZTAT Version to Mask ROM Version ................................... 476
Section 19 Clock Pulse Generator .....................................................................477
19.1 Register Descriptions ......................................................................................................... 478
19.1.1 System Clock Control Register (SCKCR) ............................................................ 478
19.1.2 Low-Power Control Register (LPWRCR) ............................................................ 479
19.2 Oscillator............................................................................................................................ 480
19.2.1 Connecting a Crystal Resonator............................................................................ 480
19.2.2 External Clock Input ............................................................................................. 481
19.3 PLL Circuit ........................................................................................................................ 483
19.4 Medium-Speed Clock Divider ........................................................................................... 483
19.5 Bus Master Clock Selection Circuit ................................................................................... 483
19.6 Usage Notes ....................................................................................................................... 484
19.6.1 Note on Crystal Resonator .................................................................................... 484
19.6.2 Note on Board Design........................................................................................... 484
Section 20 Power-Down Modes ........................................................................487
20.1 Register Descriptions ......................................................................................................... 490
20.1.1 Standby Control Register (SBYCR) ..................................................................... 490
20.1.2 Module Stop Control Registers A to C (MSTPCRA to MSTPCRC).................... 492
20.2 Medium-Speed Mode......................................................................................................... 493
20.3 Sleep Mode ........................................................................................................................ 495
20.3.1 Transition to Sleep Mode...................................................................................... 495
Rev. 7.00 Sep. 11, 2009 Page xx of xxxiv
REJ09B0211-0700