HD6417750RF240V Datasheet, PDF (89/606 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 3 MCU Operating Modes
3.2.2 System Control Register (SYSCR)
SYSCR is an 8-bit readable/writable register that selects saturating or non-saturating calculation
for the MAC instruction, selects the interrupt control mode and the detected edge for NMI, and
enables or disables on-chip RAM.
Bit Bit Name Intial Value R/W Descriptions
7
MACS
0
—
MAC Saturation
Selects either saturating or non-saturating calculation
for the MAC instruction.
0: Non-saturating calculation for the MAC instruction
1: Saturating calculation for the MAC instruction
6
—
0
—
Reserved
This bit is always read as 0 and cannot be modified.
5
INTM1
0
4
INTM0
0
R/W These bits select the control mode of the interrupt
R/W controller. For details of the interrupt control modes,
see section 5.6, Interrupt Control Modes and Interrupt
Operation.
00: Interrupt control mode 0
01: Setting prohibited
10: Interrupt control mode 2
11: Setting prohibited
3
NMIEG 0
R/W NMI Edge Select
Selects the valid edge of the NMI interrupt input.
0: An interrupt is requested at the falling edge of NMI
input
1: An interrupt is requested at the rising edge of NMI
input
2, 1 —
All 0
—
Reserved
These bits are always read as 0 and cannot be
modified.
0
RAME
1
R/W RAM Enable
Enables or disables on-chip RAM. The RAME bit is
initialized when the reset status is released.
0: On-chip RAM is disabled
1: On-chip RAM is enabled
Rev. 7.00 Sep. 11, 2009 Page 53 of 566
REJ09B0211-0700