HD6417750RF240V Datasheet, PDF (406/606 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 14 Serial Communication Interface (SCI)
nth transfer frame
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE
Retransferred frame
(DE)
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
Transfer
frame n+1
Ds D0 D1 D2 D3 D4
TDRE
TEND
FER/ERS
Transfer to TSR from TDR
Transfer to TSR from TDR
[2]
Transfer to TSR
from TDR
[3]
[1]
[3]
Figure 14.26 Retransfer Operation in SCI Transmit Mode
The timing for setting the TEND flag depends on the value of the GM bit in SMR. The TEND flag
set timing is shown in figure 14.27.
I/O data
TXI
(TEND interrupt)
When GM = 0
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE
12.5 etu
Guard
time
When GM = 1
11.0 etu
Legend:
Ds:
Start bit
D0 to D7: Data bits
Dp:
Parity bit
DE:
Error signal
Note: etu: Elementary Time Unit (time for transfer of 1 bit)
Figure 14.27 TEND Flag Generation Timing in Transmission Operation
Rev. 7.00 Sep. 11, 2009 Page 370 of 566
REJ09B0211-0700