HD6417750RF240V Datasheet, PDF (292/606 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 11 Motor Management Timer (MMT)
H'FFFF
TPDR
TGRUU
Td
TGRU
TGRUD
TCNT
2Td
1/2 period
Td
(TPBR)
2Td
H'0000
2Td
Td
Figure 11.4 Example of TCNT Count Operation
Register Operation: In the operating modes, four buffer registers and ten compare registers are
used.
The registers that are constantly compared with the TCNT counter are TGRU, TGRV, and
TGRW. In addition, TGRUU, TGRVU, TGRWU, and TPDR are compared with TCNT when
TCNT is counting up, and TGRUD, TGRVD, TGRWD are compared with TCNT when TCNT is
counting down. The buffer register for TPDR is TPBR; the buffer register for TGRUU, TGRU,
and TGRUD is TBRU; the buffer register for TGRVU, TGRV, and TGRVD is TBRV; and the
buffer register for TGRWU, TGRW, and TGRWD is TBRW.
To change compare register data, the new data should be written to the corresponding buffer
register. The buffer registers can be read and written to at all times. Data written to TPBR and the
buffer operation addresses for TBRU to TBRW is transferred at the timing specified by bits MD1
and MD0 in the timer mode register (TMDR). Data written to the free operation addresses for
TBRU to TBRW is transferred immediately.
After data transfer is completed, the relationship between the compare registers and buffer
registers is as follows:
TGRU (TGRV, TGRW) value = TBRU (TBRV, TBRW) value + Td (Td: value set in TDDR)
TGRUU (TGRVU, TGRWU) value = TBRU (TBRV, TBRW) value + 2Td
TGRUD (TGRVD, TGRWD) value = TBRU (TBRV, TBRW) value
TPDR value = TPBR value + 2Td
The values of TBRU to TBRW should always be set in the range H'0000 to H'FFFF – 2Td, and the
value of TPBR should always be set in the range H'0000 to H'FFFF – 4Td.
Rev. 7.00 Sep. 11, 2009 Page 256 of 566
REJ09B0211-0700