HD6417750RF240V Datasheet, PDF (328/606 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 12 Programmable Pulse Generator (PPG)
12.4.2 Output Timing
If pulse output is enabled, the contents of NDR contents are transferred to PODR and output when
the specified compare match event occurs. Figure 12.3 shows the timing of these operations for
the case of normal output in groups 2 and 3, triggered by compare match A.
φ
TCNT
N
N+1
TGRA
N
Compare match
A signal
NDRH
n
PODRH
m
n
PO8 to PO15
m
n
Figure 12.3 Timing of Transfer and Output of NDR Contents (Example)
Rev. 7.00 Sep. 11, 2009 Page 292 of 566
REJ09B0211-0700