HD6417750RF240V Datasheet, PDF (50/606 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 2 CPU
⎯ 16 × 16-bit register-register multiply: 4 states
⎯ 32 ÷ 16-bit register-register divide:
20 states
• Two CPU operating modes
⎯ Normal mode*
⎯ Advanced mode
• Power-down state
⎯ Transition to power-down state by SLEEP instruction
⎯ CPU clock speed selection
Note: * Normal mode is not available in this LSI.
2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU
The differences between the H8S/2600 CPU and the H8S/2000 CPU are shown below.
• Register configuration
The MAC register is supported by the H8S/2600 CPU only.
• Basic instructions
The four instructions MAC, CLRMAC, LDMAC, and STMAC are supported by the H8S/2600
CPU only.
• The number of execution states of the MULXU and MULXS instructions;
Execution States
Instruction
Mnemonic
H8S/2600
H8S/2000
MULXU
MULXU.B Rs, Rd
3
12
MULXU.W Rs, ERd
4
20
MULXS
MULXS.B Rs, Rd
4
13
MULXS.W Rs, ERd
5
21
In addition, there are differences in address space, CCR and EXR register functions, and power-
down modes, etc., depending on the model.
Rev. 7.00 Sep. 11, 2009 Page 14 of 566
REJ09B0211-0700