HD6417750RF240V Datasheet, PDF (315/606 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 11 Motor Management Timer (MMT)
11.8.4 Operation
Input Level Detection: When the input condition set in ICSR occurs on any one of the POE pins,
the MMT output pins go to the high-impedance state.
• Pins placed in the high-impedance state (the MMT’s output pins)
The 7 pins PWOB, PWOA, PVOB, PVOA, PUOB, PUOA, PCO are placed in the high-
impedance state.
Note: When used as an output port or TPU output pin, a pin will not enter the high-impedance
state.
1. Falling edge detection
When a transition from high- to low-level input occurs on a POE pin.
2. Low level detection
Figure 11.22 shows the low level detection operation. Low level sampling is performed 16
times in succession using the sampling clock set in ICSR. The input is not accepted if a high
level is detected even once among these samples.
The timing of entry of the MMT's output pins into the high-impedance state from the sampling
clock is the same for falling edge detection and low level detection.
φ
Sampling clock
POE input
PUOA
8, 16, or
128 clocks
High-impedance state
All samples low-level
[1]
At least one high-level
sample
[1]
[2]
[3]
[16] Flag set (POE accepted)
[2]
[13] Flag not set
Note: The other MMT output pins also go to the high-impedance state at the same timing.
Figure 11.22 Low Level Detection Operation
Exiting High-Impedance State: The MMT output pins that have entered the high-impedance
state are released from this state by restoring them to their initial states by means of a power-on
reset, or by clearing all the POE flags in ICSR (POE0F to POE3F: bits 12 to 15).
Rev. 7.00 Sep. 11, 2009 Page 279 of 566
REJ09B0211-0700