SH7709S Datasheet, PDF (88/807 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Table 2.8 lists the SH7709S logic operation instructions.
Table 2.8 Logic Operation Instructions
Instruction
AND Rm,Rn
AND #imm,R0
AND.B #imm,@(R0,GBR)
NOT Rm,Rn
OR Rm,Rn
OR #imm,R0
OR.B #imm,@(R0,GBR)
TAS.B @Rn
TST Rm,Rn
TST #imm,R0
TST.B #imm,@(R0,GBR)
XOR Rm,Rn
XOR #imm,R0
XOR.B #imm,@(R0,GBR)
Operation
Rn & Rm → Rn
R0 & imm → R0
(R0 + GBR) & imm →
(R0 + GBR)
~Rm → Rn
Rn | Rm → Rn
R0 | imm → R0
(R0 + GBR) | imm →
(R0 + GBR)
If (Rn) is 0, 1 → T;
1 → MSB of (Rn)
Rn & Rm; if the result
is 0, 1 → T
R0 & imm; if the result
is 0, 1 → T
(R0 + GBR) & imm;
if the result is 0, 1 → T
Rn ^ Rm → Rn
R0 ^ imm → R0
(R0 + GBR) ^ imm →
(R0 + GBR)
Code
0010nnnnmmmm1001
11001001iiiiiiii
11001101iiiiiiii
0110nnnnmmmm0111
0010nnnnmmmm1011
11001011iiiiiiii
11001111iiiiiiii
0100nnnn00011011
0010nnnnmmmm1000
11001000iiiiiiii
11001100iiiiiiii
0010nnnnmmmm1010
11001010iiiiiiii
11001110iiiiiiii
Privileged
Mode
Cycles T Bit
—
1
—
—
1
—
—
3
—
—
1
—
—
1
—
—
1
—
—
3
—
—
3
Test
result
—
1
Test
result
—
1
Test
result
—
3
Test
result
—
1
—
—
1
—
—
3
—
Rev. 5.00, 09/03, page 44 of 760