SH7709S Datasheet, PDF (328/807 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Single Read: Figure 10.16 shows the timing when a single address read is performed. As the burst
length is set to 1 in synchronous DRAM burst read/single write mode, only the required data is
output. Consequently, no unnecessary bus cycles are generated even when a cache-through area is
accessed.
Tr
CKIO
A25 to A16,
A13
A12
A15, A14,
A11 to A0
CS2 or CS3
Tc1
Td1
Tpc
RAS3x
CASx
RD/WR
DQMxx
D31 to D0
BS
Figure 10.16 Basic Timing for Synchronous DRAM Single Read
Rev. 5.00, 09/03, page 284 of 760