SH7709S Datasheet, PDF (184/807 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

6.3.7 Interrupt Request Register 1 (IRR1)
IRR1 is an 8-bit read-only register that indicates whether DMAC or IrDA interrupt requests have
been generated. This register is initialized to H'00 by a power-on reset or manual reset, but is not
initialized in standby mode.
Bit:
Initial value:
R/W:
7
TXI1R
0
R
6
BRI1R
0
R
5
RXI1R
0
R
4
ERI1R
0
R
3
DEI3R
0
R
2
DEI2R
0
R
1
DEI1R
0
R
0
DEI0R
0
R
Bit 7—TXI1 Interrupt Request (TXI1R): Indicates whether a TXI1 (IrDA) interrupt request has
been generated.
Bit 7: TXI1
0
1
Description
TXI1 interrupt request not generated
TXI1 interrupt request generated
(Initial value)
Bit 6—BRI1 Interrupt Request (BRI1R): Indicates whether a BRI1 (IrDA) interrupt request has
been generated.
Bit 6: BRI1R
0
1
Description
BRI1 interrupt request not generated
BRI1 interrupt request generated
(Initial value)
Bit 5—RXI1 Interrupt Request (RXI1R): Indicates whether an RXI1 (IrDA) interrupt request
has been generated.
Bit 5: RXI1R
0
1
Description
RXI1 interrupt request not generated
RXI1 interrupt request generated
(Initial value)
Bit 4—ERI1 Interrupt Request (ERI1R): Indicates whether an ERI1 (IrDA) interrupt request
has been generated.
Bit 4: ERI1R
0
1
Description
ERI1 interrupt request not generated
ERI1 interrupt request generated
(Initial value)
Rev. 5.00, 09/03, page 140 of 760