SH7709S Datasheet, PDF (604/807 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

17.1.4 Register Configuration
The IrDA has the internal registers shown in table 17.2. These registers select IrDA or SCIF
mode, specify the data format and a bit rate, and control the transmit and receive units.
Table 17.2 IrDA Registers
Register Name
Abbreviation R/W Initial Value Address
Access
Size
Serial mode register 1
SCSMR1
R/W H'00
H'04000140 8 bits
(H'A4000140)^*2
Bit rate register 1
SCBRR1
R/W H'FF
H'04000142 8 bits
(H'A4000142)^*2
Serial control register 1
SCSCR1
R/W H'00
H'04000144 8 bits
(H'A4000144)^*2
Transmit FIFO data register 1 SCFTDR1
Serial status register 1
SCSSR1
W
—
R/(W)^*1 H'0060
H'04000146 8 bits
(H'A4000146)^*2
H'04000148 16 bits
(H'A4000148)^*2
Receive FIFO data register 1 SCFRDR1 R
Undefined
H'0400014A 8 bits
(H'A400014A)^*2
FIFO control register 1
SCFCR1
R/W H'00
H'0400014C 8 bits
(H'A400014C)^*2
FIFO data count register 1
SCFDR1
R
H'0000
H'0400014E 16 bits
(H'A400014E)^*2
Notes: These registers are located in area 1 of physical space. Therefore, when the cache is on,
either access these registers from the P2 area of logical space or else make an appropriate
setting using the MMU so that these registers are not cached.
1. Only 0 can be written to clear the flag.
2. When address translation by the MMU does not apply, the address in parentheses
should be used.
Rev. 5.00, 09/03, page 560 of 760