SH7709S Datasheet, PDF (14/807 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Section
20.3 Bus Master
Interface
Figure 20.2 A/D Data
Register Access
Operation (Reading
H'AA40)
Page
622
Description
Figure amended
Upper byte read
CPU
receives
data H'AA
Bus
interface
Module internal data bus
TEMP
[H'40]
Lower byte read
CPU
receives
data H'40
ADDRn H
[H'AA]
ADDRn L
[H'40]
n = A to D
Bus
interface
Module internal data bus
TEMP
[H'40]
23.1 Absolute
657
Maximum Ratings
Table 23.1 Absolute
Maximum Ratings
23.2 DC
659,
Characteristics
662
Table 23.2 DC
Characteristics
ADDRn H
[H'AA]
ADDRn L
[H'40]
n = A to D
Caution added
2.Until voltage is applied to all power supplies, a low level is input
at the RESETP pin, and CKIO has operated for a maximum of 4
clock cycles, internal circuits remain unsettled, and so pin states
are also undefined. The system design must ensure that these
undefined states do not cause erroneous system operation.
Note that the RESETP pin cannot receive a low level signal while
a low level signal is being input to the CA pin.
Test conditions for in sleep mode amended
Item Symbol Min
Sleep Icc
—
mode^*1 _IccQ
—
Typ Max Unit Test Conditions
15 30
10 20
*¹: When there is no
other external bus
cycle other than the
refresh cycle.
Vcc = 1.9 V
VccQ = 3.3 V
Bφ = 33MHz
Note * added
* If the IRL and IRLS interrupts are used, the minimum is 1.9 V.
Rev. 5.0, 09/03, page xiv of xliv