SH7709S Datasheet, PDF (347/807 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Before mode register setting, a 100 µs idle time (depending on the memory manufacturer) must be
guaranteed after powering on requested by the synchronous DRAM. If the reset signal pulse width
is greater than this idle time, there is no problem in performing mode register setting immediately.
The number of dummy auto-refresh cycles specified by the manufacturer (usually 8) or more must
be executed. This is usually achieved automatically while various kinds of initialization are being
performed after auto-refresh setting, but a way of carrying this out more dependably is to set a
short refresh request generation interval just while these dummy cycles are being executed. With
simple read or write access, the address counter in the synchronous DRAM used for auto-
refreshing is not initialized, and so the cycle must always be an auto-refresh cycle.
CKIO
A15 to A13
or A15 to A12
A11
T_Rp1 T_Rp2 T_Rp3 T_Rp4 T_Mw1 T_Mw2 T_Mw3 T_Mw4
A12 or A10
A9 to A2
CSn
RD/WR
RAS3U or RAS3L
CASU or CASL
D31 to D0
CKE
(High)
Figure 10.28 Synchronous DRAM Mode Write Timing
Rev. 5.00, 09/03, page 303 of 760