SH7709S Datasheet, PDF (131/807 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Table 4.2 Exception Event Vectors
Exception Current
Type
Instruction Exception Event
Exception Vector
Priority^*1 Order
Address
Vector
Offset
Reset
Aborted Power-on reset
1
—
H'A00000000 —
Manual reset
1
—
H'A00000000 —
UDI reset
1
—
H'A00000000 —
General Aborted CPU address error 2
1
—
exception and retried (instruction access)
events
TLB miss
2
2
—
H'00000100
H'00000400
TLB invalid
2
3
—
(instruction access)
H'00000100
TLB protection
2
4
—
violation (instruction
access)
H'00000100
General illegal
2
5
—
instruction exception
H'00000100
Illegal slot instruction 2
5
—
exception
H'00000100
CPU address error 2
6
—
(data access)
H'00000100
TLB miss (data access 2
7
—
not in repeat loop)
H'00000400
TLB invalid (data
2
8
—
access)
H'00000100
TLB protection
2
9
—
violation (data access)
H'00000100
Initial page write
2
10
—
H'00000100
Completed Unconditional trap
2
5
—
(TRAPA instruction)
User breakpoint trap 2
n^*2
—
H'00000100
H'00000100
DMA address error 2
—
—
H'00000100
General Completed Nonmaskable interrupt 3
—
—
interrupt
requests
External hardware
4^*3
—
—
interrupt
UDI interrupt
4^*3
—
—
H'00000600
H'00000600
H'00000600
Notes: 1. Priorities are indicated from high to low, 1 being the highest and 4 the lowest.
2. The user defines the break point traps. 1 is a break point before instruction execution
and 11 is a break point after instruction execution. For an operand break point, use 11.
3. Use software to specify relative priorities of external hardware interrupts and peripheral
module interrupts (see section 6, Interrupt Controller (INTC)).
Rev. 5.00, 09/03, page 87 of 760