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| SH7709S Datasheet, PDF (723/807 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series | |||
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T1
Tw
Tw
TB2
TB1
Tw
TB2
T2
T2
CKIO
tAD
A25 to A4
tAD
A3 to A0
tCSD1
CSn
tRWD
RD/WE
tRSD
RD
D31 to D0
tBSD
tBSD
tRSD tAH tRSD
tRSD
tRDS1
tRDH1
tRDS1
tRDH1
tBSD
tBSD
BS
tDAKD1
DACKn
tWTS tWTH
tWTS tWTH
tAD
tAH
tCSD2 tRWH
tRDH1
tRWD
tAH
tRSD tRWH
tRDH1
tDAKD2
WAIT
Note: In the write cycle, the basic bus cycle is performed.
Figure 23.20 Burst ROM Bus Cycle (Two Waits)
Rev. 5.00, 09/03, page 679 of 760
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